The present application claims priority from Korean Application Serial No. 2001-0021363 filed Apr. 20, 2001, the disclosure of which is incorporated herein by reference as if set forth fully herein.
The present invention relates to semiconductor circuits, and more particularly, to delay locked loops.
Delay locked loops (DLLs) are clock recovery circuits for precisely synchronizing the phase of an internal clock with the phase of an external clock and are widely applied to the next generation of memories or system integrated circuits, such as synchronous dynamic random access memories (SDRAMs) or double data rate (DDR) SDRAMs.
In order to precisely synchronize the phase of an internal clock with the phase of an external clock, a phase synchronization device, such as a phase locked loop (PLL), or a DLL is typically used. Where the frequency of an external clock is different from the frequency of an internal clock, a PLL having a frequency multiplication function can be used. On the other hand, where the frequency of an external clock is the same as that of an internal clock, a DLL can be used. Unlike a PLL, a DLL, typically, does not have a problem with phase noise accumulating and, thus, is advantageous in decreasing the jitter of an internal clock. Therefore, where frequency multiplication is not necessary, it is very common to generate an internal clock using a DLL.
There are various types of DLLs including open loop type DLLs, such as synchronous mirror delays (SMDs), and closed loop type DLLs. In the case of open loop type DLLs, the locking time may be very short, but phase error may be high. Thus, it may be difficult to use the open loop type DLLs for high frequency clocks.
In order to obtain a desired delay time in a closed loop type DLL, the number of delay devices or the delay time of each of the delay devices can be adjusted. To obtain a desired delay time by adjusting the number of delay devices, a desirable delay time can be obtained by including a large number of delay devices. Such may be the case even though the frequency of an input clock varies across a wide range. For example, in order to obtain a delay time equivalent to the period of an input clock if the delay time of a delay device is 500 ps, 40 delay devices are required for an input clock with a frequency of 50 MHz, and 8 delay devices are required for an input clock with a frequency of 250 MHz. However, the accuracy of the delay time that can be adjusted is substantially equal to the delay time of a delay device, that is, 500 ps, and, thus, it may be very difficult to precisely adjust phase.
In a DLL using a large number of delay devices, the delay time of a delay device becomes the minimum locking resolution of the DLL. Thus, in order to obtain precise locking characteristics, the delay time of a delay device should be small. However, in order to sufficiently cover a maximum operation clock cycle time, the number of delay devices should be large. Thus, the length of a delay line consisting of the delay devices increases. Accordingly, increased layout area and power consumption may result. For example, if a maximum operation clock period is 20 ns, at least 1000 delay devices may be required to ensure a locking resolution of 20 ps.
When a desired delay time is provided by adjusting the delay time of each delay device, the accuracy of the delay time that can be adjusted can be considerably enhanced. For example, by adjusting the delay time using an analog voltage, an infinitely great accuracy can theoretically be obtained. However, the range in which the delay time of a delay device can be adjusted is limited, and thus, where the frequency of an input clock varies across a wide range, a desired delay time may be unattainable. For example, where there are 20 delay devices, and the delay time of one of the twenty delay devices varies between 200 ps and 500 ps, in order to obtain a delay time equivalent to the period of an input clock, one of the twenty delay devices must have a delay time of 1 ns for an input clock with a frequency of 50 MHz; however, a delay time of 1 ns is beyond the delay time range of the delay devices.
Embodiments of the present invention provide a delay locked loop according to the present invention including a phase detector, a delay line, and a delay time adjuster. The phase detector is configured to compare the phase of the reference clock signal with the phase of the feedback clock signal and outputting a value corresponding to a difference between the phase of the reference clock signal and the phase of the feedback clock signal as an error control signal. The delay line includes a plurality of first delay devices having a fixed delay time, selectively connected in series, and configured to adjust the number of first delay devices connected in series in response to a shift signal and to generate an output clock signal in response to an input clock signal. The delay time adjuster is configured to receive the reference clock signal and variably delay the reference clock signal in response to the error control signal to generate the input clock signal and the shift signal.
In further embodiments of the present invention, a delay compensation circuit is configured to compensate for the phase difference between the output clock signal and the feedback clock signal.
In additional embodiments of the present invention, the delay time adjuster includes a variable delay device configured to receive the reference clock signal and variably delay the reference clock signal in response to the error control signal so as to generate a variable delay signal. A maximum variable delay device is configured to receive the reference clock signal and delay the reference clock signal by a delay amount corresponding to the maximum delay time of the variable delay device to generate a maximum delay clock signal. A minimum variable delay device is configured to receive the reference clock signal and delay the reference clock signal by a delay amount corresponding to the minimum delay time of the variable delay device to generate a minimum delay signal. A multiplexer selects one signal from the variable delay signal, the maximum delay clock signal, and the minimum delay signal as the input clock signal. A controller is configured to compare a variable delay clock signal, generated by delaying the variable delay signal the fixed delay time, with the maximum delay clock signal and a minimum delay clock signal, generated by delaying the minimum delay signal twice the fixed delay time, to generate a shift signal and a selection signal that controls the multiplexer.
Additionally, the fixed delay time of the first delay devices may be less than a difference between the maximum delay time to which the maximum variable delay device delays the phase of the reference clock signal and the minimum delay time to which the minimum variable delay device delays the phase of the reference clock signal. The controller may be further configured to control the shift signal to increase the number of first delay devices by one if the variable delay clock signal is behind the minimum delay clock signal and control the shift signal to decrease the number of first delay devices by one if the variable delay clock signal is ahead of the maximum delay clock signal. The controller may also be configured to control the selection signal to select the minimum delay signal as the input clock signal when the shift signal is controlled to increase the number of first delay devices by one and to control the selection signal to select the maximum delay clock signal as the input clock signal when the shift signal is controlled to decrease the number of first delay devices by one.
In still further embodiments of the present invention, each of the first delay devices in the delay line receives the input clock signal and a first input signal, selects one signal from the input clock signal and the first input signal, and supplies the selected signal to the next first delay device as the first input signal. The output of a final first delay device in the delay line is generated as an output clock signal.
In other embodiments of the present invention, a delay locked loop including a delay line in which a plurality of first delay devices having a fixed delay time are connected in series. The phase of a reference clock signal is compared with the phase of a feedback clock signal and the phase difference between the reference clock signal and the feedback clock signal output as an error control signal. An input clock signal is provided to the delay line by receiving the reference clock signal and variably delaying the reference clock signal in response to the error control signal. A shift signal for controlling the number of first delay devices connected in series is generated and an output clock signal is generated utilizing the delay line based on the input clock signal and the shift signal.
The input clock signal may be generated by variably delaying the reference clock signal in response to the error control signal to provide a variable delay signal. The reference clock signal is delayed by as much as the maximum delay time to which the variable delay signal can be delayed to provide a maximum delay clock signal. The reference clock signal is also delayed by as much as the minimum delay time to which the variable delay signal can be delayed to provide a minimum delay signal. The variable delay clock signal, generated by delaying the variable delay signal an amount corresponding to the delay of one of the first delay devices to delay the variable delay signal, is compared with the maximum delay clock signal and a minimum delay clock signal, generated by delaying the minimum delay signal an amount corresponding to a delay of two of the first delay devices to delay the minimum delay signal, and a shift signal and a selection signal generated. One signal from the variable delay signal, the maximum delay clock signal, and the minimum delay signal is selected in response to the selection signal to provide the selected signal as the input clock signal.
Furthermore, a number of first delay devices utilized in the delay line may be increased by one if the variable delay clock signal is behind the minimum delay clock signal. The minimum delay signal is selected as the input clock signal if the variable delay clock signal is behind the minimum delay clock signal. The number of first delay devices utilized in the delay line may be decreased by one if the variable delay clock signal is ahead of the maximum delay clock signal. The maximum delay clock signal is selected as the input clock signal if the variable delay clock signal is ahead of the maximum delay clock signal.
Additionally, a fixed delay time of the first delay devices may be less than the difference between the maximum delay clock signal and the minimum delay signal.